Demand for electronic devices capable of implementing ever more numerous functions has led toward chips with an ever increasing number of connection pins. As a consequence, the time required for testing monolithically fabricated devices on a silicon wafer has increased proportionally with the number of pins of each device. Typically, there may be about 500 memory chips realized on a single 8-inch wafer and it is evident that verifying one memory chip at the time would require too much time.
For this reason, techniques have been devised for parallel testing the individual chips on the wafer. In practice, test devices having a plurality of conducting probes are used. The tips of the probes are in contact with different pads of a plurality of devices realized on wafer, and through them the test system may simultaneously feed test signals to a plurality of devices and verify that their responses satisfy the specifications.
In case of devices with numerous contacting pads, it may become impossible to carry out tests on wafer of many chips in parallel because these test systems have a limited number of probes. It is thus important to limit the number of pads of integrated devices. The so-called LPC (Low Pin Count) devices satisfy this requisite because though their input and output pads signals are transferred in serial mode signals. In practice, through input/output pads of an LPC device commands and information may be exchanged with the external world. Packaged LPC memory devices may have up to 80 pins or more and the chip may have only about 15 pads. With LPC electronic devices it is possible to remarkably reduce the number of probes necessary for testing on wafer the functioning of each device and thus the number of devices that may be tested at the same time.
Generally, electronic devices have at least an array of input pads and an array of output pads. Often, because of design constraints, it is necessary to replicate in each of these arrays of pads a certain number of pads having the same function. For instance, it may happen that circuits physically integrated distant one from the other must be input with a same external signal (for instance a clock signal). In theory, it would be possible to feed this signal only on one pad of the device and then distribute it to different circuits through an internal line, but this would slow down the functioning of the device and could generate synchronization problems because of propagation delays along the internal line.
To achieve maximum speed of the device, replica pads are realized for providing a same external signal physically close to the respective circuits that use it. FIG. 1 shows by way of example this situation in which the clock pad CLK has been replicated in each of the four arrays or groups of pads of the chip. These replica pads are realized on respective connection balls of the package through a bonding operation. Commonly, they are connected to an input buffer of the device IN_BUFFER through a protection block ESD PROT against accidental electrostatic discharges.
During test operations, each of these replicated pads must be contacted by a respective probe. Understandably, the more numerous the replicated pads are, the fewer are the chips that may be tested at the same time by the test system. It would be desirable that the number of probes necessary to test an electronic device were independent from the number of replicated pads of the devices.